Model & simulate
Capture specs, SystemVerilog TBs, cocotb/questa runs, trace instrumentation.
Capabilities
Where I create leverage
Select a track to see how I approach it.
Tap a capability to see my approach.
Design pillars
Signal-first thinking
Every build starts with budgets: clocks, power, routing, verification closure, and instrumentation that makes deterministic systems debuggable.
- Hardware/software co-design Partitioning functionality across FPGA fabric, firmware, and host services.
- Deterministic latency Careful CDC, timing reports, and link-level instrumentation.
- Observability + tooling Python/C++ harnesses, on-chip analyzers, CI-friendly testbenches.
Build loop
Prototype & measure
Bring-up on dev boards, microbenchmarks, python notebooks for latency reports.
Iterate & harden
Floorplanning, CDC review, firmware polish, documentation, and roll-out.
Selected snapshots
Projects & experiments
Latency lab
Instrumentation + research playground
I keep a standing lab of replay harnesses, PTP-enabled switches, and FPGA dev boards to validate ideas fast. Want to explore a concept or benchmark a path? Tap below and let's simulate the burst together.
Experiments triggered
0Toolbox & languages I lean on
SystemVerilog
Verilog/VHDL
Python (cocotb)
C / C++
Rust (tools)
Vivado / Quartus
SmartNIC SDKs
FIX / PTP
Git + CI
Linux bring-up